This invention relates generally to flash electrically erasable and programmable read only memories (EEPROMS), and, more specifically, to such memories with a very high density of cells, particularly when operated with more than two threshold states (termed "multi-state" or "multi-level" operation) to store more than one bit of data in each cell.
Most existing commercial flash EEPROM products operate each memory cell with two ranges of threshold voltages, one above and the other below a breakpoint level, thereby defining two programmed states. One bit of data is thus stored in each cell, a 0 when programmed into one state and a 1 when programmed into its other state. A chunk of a given number of bits of data is programmed at one time into an equal number of cells. The state of each cell is monitored during programming so that application of programming voltages stops when the threshold level an individual cell is verified to have moved within the range that represents the value of the bit of data being stored in the cell.
In order to increase the amount of data stored in a flash EEPROM system having a certain number of storage cells, the individual cells are operated with more than two threshold level states. Preferably, two or more bits of data are stored in each cell by operating the individual cells with four or more programmable states. Three threshold breakpoint levels are necessary to define four different threshold states. Such a system is described in U.S. Pat. Nos. 5,043,940 and 5,172,338, which are being incorporated herein by this reference. In multi-state operation, an available operating voltage range of the individual cells is divided into an increased number of states. The use of eight or more states, resulting in storing three or more bits of data per cell, is contemplated. The voltage range of each state necessarily becomes smaller as the number of states is increased. This leaves less margin within each state to accommodate any error that might occur during operation of the memory system.
One type of error is termed a "disturb," wherein electrons are unintentionally added to or taken away from a floating gate during operation of the memory. One source of a disturb is the presence of a leaky oxide dielectric positioned between the floating gate and another conductive gate of a cell. The charge level programmed onto a floating gate of a cell changes when such a leaky oxide is present, thus leading to the possibility that the state of the cell will be incorrectly read if the change in charge has been large enough. Since few to no errors can be tolerated in a mass digital data storage system, a sufficient margin for this error is provided by making the voltage range allocated to each state sufficient to include an expanded range of voltages that can occur as the result of such disturbs. This necessarily limits the number of states that can be included in a multi-state flash EEPROM system since the total available voltage range is limited.
It is a general object of the present invention to provide flash EEPROM structures and operating techniques that improve the accuracy of data stored in and read from the memory, particularly when operating in a multi-state mode.
It is a more specific object of the present invention to shrink the size of a flash EEPROM array of cells on an integrated circuit chip without adversely affecting the ability to accurately program and read the memory, particularly when operating in a multi-state mode.